// Linear-Feedback Shift Register
module lfsr(rst, clk, out);
  input rst;
  input clk;
  output reg [7:0] out;

  reg out_top;

  always @(posedge clk)
    if (rst) out <= 1;
    else begin
      out_top = out[4] ^ out[3] ^ out[2] ^ out[0];
      out <= {out_top, out[7:1]};
    end

endmodule
